1. Field of the Invention
The present invention relates, in general, to a method for the fabrication of semiconductor device and, more particularly, to prevention of a short circuit between a silicon substrate and a metal wiring, which may occur when the metal wiring comes into contact with a conductive wiring.
2. Description of the Prior Art
High integration of DRAM cell requires that patterns be as fine as possible, and therefore, the process margin becomes reduced of minimum degree upon layout. Accordingly, there is great difficulty in the alignment for, inter alia, fine contacts,
In order to better understand the background of the present invention, a conventional semiconductor memory device will be generally described, along with its fabrication process, in connection with some figures.
With reference to FIG. 1, there is a layout showing a contact of metal wirings with gate electrode. As shown in this figure, a an extended gate electrode region 4 which constitutes a MOSFET, along with a source region 5 and a drain region 6 comes into contact with a metal wiring 10 at a contact region 20 formed at an edge area of the extended gate electrode region 4. In this layout, there is shown a misalignment that the contact region 10 is overlapped with the gate electrode 4, when contact masks are aligned.
Referring to FIG. 2. there is a cross section illustration a prior technique for forming a contact of metal wiring, taken generally through line I--I of FIG. 1. For the contact according to the prior technique a field oxide layer 2 is first formed on an area of a silicon substrate 1 and then, a gate oxide layer 3 is grown on an active region of the silicon substrate. Thereafter, a gate electrode 4 is formed on the gate oxide layer 3 in such a way that it should extent over, overlapping with the field oxide layer 2. Subsequently, a blanket interlayer insulation film 7 is deposited over the resulting structure. Thereafter, the interlayer insulation film 7 is subjected to selective etch by means of a contact mask to form a contact hole, followed by formation of a metal wiring 10.
It should be noted that the field oxide is exposed by a misalignment of the contact mask and thus, etched upon the selective etch. As a result, the contact hole formed exposes the silicon substrate, which causes the metal wiring to come into undesired contact with the silicon substrate. Consequently, the resulting semiconductor device fabricated by the prior technique becomes defective.